The JSON Product file describes a product in great detail. It is intended for import into a price calculation system, in order to quickly calculate the price for a product.
At this time, the content of the file is still under development. Although many parameters are already included, we welcome feedback about additional parameters, as desired. Contact us at support@macaos.com with your requests and suggestions.
The file has the following form:
{
"macaosProduct": { properties }
"macaosRfq": { properties }
}Each object in the file consists of multiple properties, as specified below. Some properties are only specified when appropriate for the context. Unspecified properties should be treated as not applicable, not specified or unknown.
Note: Support for the macaosRfq object has not yet been fully implemented.
macaosProduct
The macaosProduct properties are:
| productTypeId | Example value | Units | Product type | Additional comments |
|---|---|---|---|---|
| productTypeId | 1 | Product type | 1=rigid, 5=flex, 9=rigid-flex, 13=metal-based; +2=panel, +3=multi-product panel | |
| productId | 329818 | Macaos internal system identifier | ||
| productNo | 267976 | Macaos product number | ||
| name | 401119_v1.0.0_Panel_0499RUBR | Product name | ||
| prodTypeDesc | Printed Circuit Board | Product type description | ||
| tariffCode | 85 34 00 00 00 (bare printed circuit boards) | Product tariff code | ||
| publisherId | 10810 | Macaos internal system identifier | ||
| sizeX | 98.999 | mm | Product X dimension | |
| sizeY | 118.0008 | mm | Product Y dimension | |
| styleID | 8021 | Macaos internal buildup code | ||
| styleName | 8021: Custom build | Macaos buildup description | ||
| matlCmt | Description of other finish or color | Only if needed | ||
| layers | 8 | Copper layer count | ||
| buildup | 1519=P 18 1x1080-p 35 1x1080-p 35 1x1080-p 35 889-c 35 1x1080-p 35 1x1080-p 35 1x1080-p 18 P|[\"FR-4 Mid-Tg^4101/24^150^N^^EM-827\"] | Macaos buildup specification | See buildup description below | |
| finishId | 3 | Surface finish code | 2=None, 3=ENIG gold (Ni/Au), 4=Immersion silver, 5=Immersion tin, 6=Lead-free HASL [2-40um], 7=Soft gold (wire bondable), 8=OSP, 9=Plated gold (electrolytic), 10=HASL (non-RoHS), 11=Other, 12=ENEPIG gold (Ni/Pd/Au) | |
| solderTopId | 6 | Solder mask top color code | 2=None, 3=Black, 4=Blue, 5=White, 6=Green, 7=Yellow, 8=Red, 9=Brown, 10=Other | |
| solderBotId | 6 | Solder mask bottom color code | 2=None, 3=Black, 4=Blue, 5=White, 6=Green, 7=Yellow, 8=Red, 9=Brown, 10=Other | |
| legendTopId | 5 | Legend top color code | 2=None, 3=Black, 4=Blue, 5=White, 6=Green, 7=Yellow, 8=Red, 9=Brown, 10=Other | |
| legendBotId | 5 | Legend bottom color code | 2=None, 3=Black, 4=Blue, 5=White, 6=Green, 7=Yellow, 8=Red, 9=Brown, 10=Other | |
| goldAreaTop | 0 | cm² | Hard/finger gold area on top side | |
| goldAreaBot | 0 | cm² | Hard/finger gold area on bottom side | |
| peelOffTop | false | Has peelable mask on top side | ||
| peelOffBot | false | Has peelable mask on bottom side | ||
| depthRoutTop | false | Has depth routing on top side | ||
| depthRoutBot | false | Has depth routing on bottom side | ||
| stiffenerTop | false | Has stiffener on top side | Flex or rigid-flex products only | |
| stiffenerBot | true | Has stiffener on bottom side | Flex or rigid-flex products only | |
| coverLayerTop | 3 | Cover layer top color code | Flex or rigid-flex products only. 2=None, 3=Natural (Yellow), 4=Black, 5=White, 6=Other | |
| coverLayerBot | 3 | Cover layer bottom color code | Flex or rigid-flex products only. 2=None, 3=Natural (Yellow), 4=Black, 5=White, 6=Other | |
| flexLayers | 2 | Qty flexible layers | Rigid-flex products only | |
| minTCond | 01.05.2026 | W/m-K | Meetal thermal conductivity | MBB products only |
| viaFilling | 7 | Via filling type | 0=None, 1=Tented, 2=Tented/Covered, 3=Plugged, 4=Plugged/Covered, 5=Filled, 6=Filled/Covered, 7=Filled/Capped | |
| carbon | false | Has carbon print | ||
| kapton | false | Has kapton (or similar) tape | ||
| halfMoon | false | Has castellated holes | ||
| scoring | false | Has scoring (V-cut) | ||
| countersink | false | Has countersink holes | ||
| microvias | true | Has microvias | Diameter<0.25 mm, Aspect ratio<1:1 | |
| pressFit | false | Has press-fit holes | ||
| platedSlots | false | Has plated slots | ||
| edgeConn | false | Has edge connector | ||
| bevel | false | Has beveled edge | ||
| bevelAngle | degrees | Angle of bevel (from board surface) | Only if bevel is true | |
| bevelBackoff | µm | Distance from board edge to start of cut | Only if bevel is true | |
| hasUL | false | UL mark required | ||
| holesPT | 2744 | Plated through holes | ||
| toolsPT | 1 | Plated through tools | ||
| holesNP | 106 | Non-plated through holes | ||
| toolsNP | 3 | Non-plated through tools | ||
| holesBT | 462 | Blind top side holes | ||
| toolsBT | 1 | Blind top side tools | ||
| holesBB | 0 | Blind bottom side holes | ||
| toolsBB | 0 | Blind bottom side tools | ||
| holesBuried | 536 | Buried via holes | ||
| holesLaser | 998 | Laser drilled holes | ||
| holesMech | 2850 | Mechanical drilled holes | ||
| buriedDepths | 2 | Quantity buried via depths | ||
| backDrillDepths | 0 | Quantity backdrill depths | ||
| minThru | 200 | µm | Minimum through hole diameter | |
| minBlind | 100 | µm | Minimum blind via diameter | |
| minBuried | 100 | µm | Minimum buried via diameter | |
| minMech | 200 | µm | Minimum mechanical hole diameter | |
| holeDensity | 2835 | #/dm² | Average holes/dm² for entire board | |
| depthRoutCnt | 0 | Depth routed slot count | ||
| routQty | 13 | Routed slot count | Includes outer profile and depth routed slots | |
| minRout | 1600 | Minimum rout tool diameter | ||
| routLength | 0.764 | m | Total rout length | |
| countersinkCnt | 0 | Countersink hole count | ||
| trackO | 93 | µm | Minimum line width outer layers | |
| trackI | 93 | µm | Minimum line width inner layers | |
| clearO | 93 | µm | Minimum spacing outer layers | |
| clearI | 93 | µm | Minimum spacing inner layers | |
| ringO | 50 | µm | Minimum annular ring outer layers | pad radius – hole radius |
| ringI | 50 | µm | Minimum annular ring inner layers | pad radius – hole radius |
| minHoleClear | 200 | µm | Minimum spacing Cu-unplated edge | |
| brdsOnPanel | 1 | Qty boards per panel | ||
| prodsOnPanel | 1 | Qty different boards per panel | ||
| boardArea | 1.1682 | dm² | Area of board | |
| area | 1.1682 | dm² | Area of bound box | Bound box = sizeX * sizeY |
| testPtTop | 862 | Test point count on top side | Taken from IPC-D-365 data (if available); otherwise from analysis of solder mask openings with exposed copper | |
| testPtBot | 469 | Test point count on bottom side | Taken from IPC-D-365 data (if available); otherwise from analysis of solder mask openings with exposed copper | |
| drillDepths | 4609,4626,736,766 | List of Macaos layer ids for drill depths | ||
| weight | 61 | g | Estimated weight | |
| ipcClass | 2 | IPC-601x performance class | Class 4 is defined by us as IPC class 3 requirements for hole wall plating and annular ring; and class 2 requirements for other parameters | |
| holePlating | 20 | µm | Minimum hole wall plating thickness | |
| impCtl | true | Requires impedance control | ||
| noShave | false | Copper shaving is not allowed | ||
| eltest | true | Requires electric test | ||
| prohibitMark | false | Fabricator markings not allowed | ||
| cuExposed | 2.8565 | cm² | Exposed copper area for surface finish | Includes calculated surface area of hole walls |
| cuExposedPct | 2.445 | % | Exposed copper % of bound box area | Bound box = sizeX * sizeY |
| platingCount | 3 | Qty plating cycles | ||
| pressingCount | 3 | Qty lamination cycles | ||
| asymmetric | false | Has asymmetric buildup | ||
| sequentialBuild | true | Has sequential buildup | ||
| stackedVias | false | Has stacked vias | ||
| coreCount | 1 | Qty dielectric cores | ||
| prepregCount | 2. | Qty prepreg sheets | If a layer is specified as e.g. 2x1080, then that layer contributes 2 to prepregCount |
macaosRFQ
The macaosRfq properties are:
| productTypeId | Example value | Units | Product type | Additional comments |
|---|---|---|---|---|
| customer | Elprint As | Name of customer | ||
| quantity | 100 | pcs | Qty items ordered | If panel, then qty is panel qty (not single board qty) |
| leadTime | 10 | days | Lead time in working days | Production days after all engineering questions have been resolved. Does not include holidays or shipment time. Ignored if shipDate is specified. |
| shipDate | 2026-09-28 | Desired shipment date from supplier | If specified, takes precedence over leadTime |
Buildup description
The buildup property specifies a compact buildup description (CBD) of the PCB. A CBD is a single-line description of the detailed layer buildup. It consists of four parts with separator characters:
- Thickness in µm
- =
- Layer specification (space-separated)
- | (only if dielectric material is specified)
- Dielectric material (optional; default is FR-4 IPC-4101C/21)
- { (only if thickness tolerance is specified)
- Thickness tolerance
The layer specification is a space separated list of thicknesses and optional modifiers. In most cases, the layers alternate between copper and dielectric layers. Other layer types (including plating) do not affect the layer alternation. For 2 or more copper layers, the alternation begins with copper, otherwise it begins with dielectric.
Copper layers
Copper layers are specified in µm, as base copper without plating.
For copper layers which require plating (for holes and vias), a "P" layer is placed either above or below the copper layer specification. P is interpreted as 12µm for Type 1 or 2 flexible PCBs, 20µm for IPC class 1 or 2, or otherwise 25µm.
Options may be attached to a copper layer with a hyphen. Valid options are f=flexible, and i=impedance critical. For example, 18-f indicates a ½ oz flexible layer.
Dielectric layers
Dielectric layers are specified in one of three ways:
- a free thickness, to be determined by the manufacturer, is specified as: x
- a nominal thickness is specified as an integer value in µm, such as 1550 or 280
- a prepreg sheet combination may be specified as NxGGGG where N is a sheet count and GGGG is a woven glass type. For example: 1x2116 or 1x1080+1x7628.
Options may be attached to a dielectric layer with a hyphen. Valid options are c=core, p=prepreg, f=flexible, and i=impedance critical. For example, 720-ci indicates a 0.72 mm core where the thickness is impedance critical.
If a dielectric layer material differs from the material specified for the buildup, it is specified (after any options) following a } separator.
Other layer types
- SM: Solder mask. Only specified when necessary for a non-standard material or process. May include material description.
- 75-l or x-l: Cover layer. Thickness in µm or x for supplier-determined thickness. Only specified when necessary for a non-standard material or process. May include material description.
- 254-s or x-s: Stiffener. Thickness in µm or x for supplier-determined thickness.
- 50-a or x-a: Adhesive. Thickness in µm or x for supplier-determined thickness. Only specified when necessary for a non-standard material or process; not usually specified for cover layer, since adhesive is normally treated as part of the cover layer. May include material description.
Material descriptions
Material descriptions are enclosed in [" "] and include several fields separated by ^ characters. The fields are:
- Description
- IPC slash seet
- Tg (degrees)
- Halogen free (Y or N)
- Manufacturer
- Additional info
